Dr. José Raúl Loo Yau

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Publicaciones

Publicaciones en Revista Arbitradas
 
2015
 
M. A. Pulido-Gaytan, J. Apolinar Reynoso-Hernandez, J. R. Loo-Yau, A. Zarate-de Landa, M. del Carmen Maya-Sanchez, “Generalizad Theory of the Thru-Reflect-Match Calibration Technique, “ IEEE Transaction on Microwave Theory and Techniques, Vol. 63, No 5, pp. 1693-1699, May 2015, DOI: 10.1109/TMTT.2015.2417860
 

J. R. Loo-Yau, I. Tapia-Sánchez, P. Moreno, “An alternative method to extract the parasitic capacitances of GaN FETs,” Microwave Optical Technology Letters, Vol. 57, No 1, pp. 223-225, January 2015, ISSN: 0895-2477, DOI: 10.1002/mop.28816.

2014

H. J. Saavedra-Gomez, J. R. Loo-Yau, Juan Luis del Valle-Padilla, P. Moreno, F. Sandoval-Ibarra, J. A. Reynoso-Hernandez, “Enhanced RF characterics of a 0.5 μm High Voltage nMOSFET (HVMOS) in a standard CMOS Technology,” Journal of Applied Research and Technology, Vol. 12, No 3, pp. 471-476, 2014, ISSN: 1665-6423.

 2013

H. J. Saavedra-Gomez, J. R. Loo-Yau, J. A. Reynoso-Hernandez, P. Moreno, F. Sandoval-Ibarra, S. Ortega-Cisneros, “A Simple De-embedding Method for On-Wafer RF CMOS FET Using Two Microstrip Lines,” Revista Mexicana de Física, Vol. 59, No. 6, pp. 570-576, Nov-Dec. 2013, ISSN: 0035-001X.

H. J. Saavedra-Gomez, J. R. Loo-Yau, J. A. Reynoso-Hernandez, P. Moreno, Juan Luis del Valle-Padilla, “A Simple and Reliable Method to Extract the Electrical Equivalent Circuits of CMOS Pads,” Microwave Optical Technology Letters, Vol 55, No 12, pp.3033-3037, December 2013, ISSN: 0895-2477, DOI: 10.1002/mop.27967.

M. A. Pulido-Gaytán, J. A. Reynoso-Hernández, A. Zárate-de Landa, J. R. Loo-Yau, M. C. Maya-Sáncehz, “Vector Network Analyzer Calibration Using a Line and Two Offset Reflecting Loads,”  IEEE. Trans. on Microwave Theory and Tech., Vol. 61, No 9, pp. 3417-3423, September 2013, ISSN: 0018-9480, DOI: 10.1109/TMTT.2013.2275471.

2012
 
A. Zarate de Landa, P. Roblin, J. A. Reynoso-Hernández, J. R. Loo-Yau, “Modeling the I-V Curves and Its Derivatives of Microwave Transistors Using Neural Network,” IEEE Microwave and Wireless Components Letters, Vol. 22, No 9, pp. 468-470, September 2012. ISSN: 1531-1309, DOI: 10.1109/LMWC.2012.2210866.

2011

J. R. Loo-Yau, O. I. Gómez-Pichardo, F. Sandoval-Ibarra, M. C. Maya-Sánchez, J. A. Reynoso-Hernández, “Enhancement of the Rejection Bandwidth of Microwaves Coupled Lines Filters Using Spurline Structures,” Microwave Optical Technology Letters, Vol. 53, No. 12, pp. 2893-2896, December 2011.

J. E. Zuñiga-Juárez, J. A. Reynoso-Hernández, J. R. Loo-Yau, M. C. Maya-Sánchez, “An Improved Two-Tier L-L Method for Characterizing Symmetrical Microwaves Test Fixtures,” ELSEIVER Measurements 44, pp. 1491-1498, 2011.

J. R. Loo-Yau, O. I. Gómez-Pichardo, F. Sandoval-Ibarra, M. C. Maya-Sánchez, J. A. Reynoso-Hernández, “Spurline Structures and its Application on Microwave Coupled Line Filter,”  Revista Mexicana de Física, Vol. 57, No 3, pp. 184-187, June 2011.

A. García-Osorio, J. R. Loo-Yau, J. A. Reynoso-Hernandez, Susana Ortega-Cisneros and J. L. del Valle-Padilla, “An Empirical I-V Nonlinear Model Suitable for GaN FET Class F PA Design,” Microwave Optical Technology Letters, Vol. 53, No 6, pp.1256 - 1259, June 2011. 

2009

Andrés Zaráte-de Landa, J. E. Zuñiga-Juárez, J. A. Reynoso-Hernández, M. C. Maya-Sánchez, Juan Luis del Valle-Padilla, J. R. Loo-Yau,Advances in Linear Modeling of Microwave Transistors,” IEEE Microwave Magazine, vol. 10, No 2, pp. 100, 102 - 111, 146, April 2009.

2007

 J. R. Loo-Yau, Hugo Ascencio-Ramírez and J. A. Reynoso-Hernández, “An Extensión of the Classical Method to Design High Efficiency Microwave Class E PA´s,” IEEE Microwave Wireless Components Letters, vol. 17, No 7, pp. 540-542, July 2007.

2006 

 J. R. Loo-Yau, J. A. Reynoso-Hernández, J. E. Zuñiga, F. I. Hirata-Flores and Hugo Ascencio-Ramírez, “Modeling the I-V Characteristic of The Power Microwave FET with the Angelov Model using Pulse Measurements.” Microwave Optical Technology Letters, Vol 48, No 8, June 2006.

 J. R. Loo-Yau, Hugo Ascencio-Ramírez and J. A. Reynoso-Hernández, “DC or Pulse I(V) Measurements to Simulate Transmission Line Class E Power Amplifier.” Microwave Optical Technology Letters, Vol.48, No 9, September 2006.

Publicaciones en Congresos Internacionales

 2015

Lina. M. Aguilar-Lobo, J. R. Loo-Yau, S. Ortega-Cisneros, P. Moreno, J. A. Reynoso-Hernandez, “Experimental Study of the Capabilities of the Real Valued NARX Neural Network for Behavioral Modeling of Multi-Standard RF Power Amplifier,” IEEE International Microwave Simposium, Phoenix, Arizona, 2015.

J. A. Reynoso-Hernandez, Jaqueline Estrada-Mendoza, M. C. Maya-Sanchez, M. A. Pulido-Gaytan, J .R. Loo-Yau, J. E. Zuñiga-Juarez, Juan Luis del Valle-Padilla, “A New Method for Extracting Ri and Rgd of the Intrinsic Transistor Model of GaN HEMT Based on Extrema Points of Intrinsic Y-Parameters,” IEEE International Microwave Simposium, Phoenix, Arizona, 2015.

M. A. Pulido-Gaytán, J. A. Reynoso-Hernández, M. C. Maya-Sánchez, A. Zarate-de Landa, J. R. Loo-Yau, “On the implementation of the LZZ calibration technique in the S-parameters measurement of devices mounted in test fixtures,” in 85th Automatic Microwave Measurement Conference (ARFTG), Phoenix, Arizona, May 2015.

2014

J. R. Loo-Yau, “Modelado de las capacitancias parásitas en los transistores FET de Nitruro de Galio”, XXXIV Convención de Centro América y Panamá CONCAPAN, pp. 1-6, Panamá, Panamá, 2014.

J. Urbina-Martínez, J. R. Loo-Yau, P. Moreno, “La nueva tendencia en la caracterización de dispositivo no lineales de RF”, XXXIV Convención de Centro América y Panamá CONCAPAN, pp. 1-6, Panamá, Panamá, 2014.

J. A. Renteria-Cedeno, L. M. Aguilar-Lobo, J. R. Loo-Yau, S. Ortega-Cisneros, “Implementation of a NARX neural network in a FPGA for modeling the inverse characteristics of power amplifiers,” in in IEEE 57th International Midwest Symposium on Circuit and Systems, pp. 209-212, College Station, TX, 2014.

L. M. Aguilar-Lobo, A. Garcia-Osorio, J. R. Loo-Yau, S. Ortega-Cisneros, P. Moreno, J. E. Rayas-Sánchez, J. A. Reynoso-Hernandez, “A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers,” in IEEE 57th International Midwest Symposium on Circuit and Systems, pp. 717-720, College Station, TX, 2014.

M. A. Pulido-Gaytan, J. A. Reynoso-Hernandez, A. Zarate-de Landa, J. R. Loo-Yau, “LZZM: An extension of the theory of the LZZ calibration technique,” in 84th ARFTG Microwave Measurement Conference, pp 1-5, Boulder, CO, 2014.

J. R. Loo-Yau, P. Moreno, J. A. Reynoso-Hernández, M. C. Maya-Sanchez, “Microwave research collaboration between Cinvestav-GDL and CICESE, two research center in Mexico,” in IEEE International Microwave Symposium, pp. 1-4, Tampa, Florida, 2014.

2013

A. Zarate-de Landa, J. A. Reynoso-Hernandez, P. Roblin, M. A. Pulido-Gaytan, J. R. Loo-Yau, “A Neural Network Approach to Smooth Calibrated Data Corrupted from Switching Errors,” in 82nd ARFTG Microwave Measurement Conference, DOI: 10.1109/ARFTG-2.2013.6737341, Columbus, OH, 2013.

A. García-Osorio, J. R. Loo-Yau, P. Moreno, L. Ilich Guerrero-Linares, J. A. Reynoso-Hernandez, “A Simple Procedure to Synthesize Input and Output Matching Networks with Short Stub for Class F-1 PAs,” in IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, 2013.

J. A. Reynoso-Hernández, M. A. Pulido-Gaytán, A. Zarate-de Landa, J. R. Monjardin-Lopez, J. E. Zuñiga-Juarez, A. Garcia-Osorio, D. Orozco-Navarro, J. R. Loo-Yau, M. C. Maya-Sanchez, “Using Lines of Arbitrary Impedance as Standards on the TRL Calibration Technique,” in 81th ARFTG Conference, Seattle, WA, 2013.

2012

A. Zaráte-de Landa, M. A. Pulido-Gaytán, J. A. Reynoso-Hernandez, P. Roblin, J. R. Loo-Yau, “A Neural Network Approach to Smooth Calibrated Data Corrupted from Switching Errors, in 80th ARFTG Conferences, San Diego, CA, 2012.

L. Guerrero-Linares, F. Sandoval-Ibarra, J. R. Loo-Yau, “Non-idealities in Analog Circuits Design: What does it really means?,” in IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, 2012.

H. J. Saavedra-Gómez, J. R. Loo-Yau, B. E. Figueroa-Resendiz, J. A. Reynoso-Hernández, “On Wafer CMOS Transistors De-Embedding Method Using Two Lines of Different Lengths,” Accepted to the Radio Frequency Integrated Circuit (RFIC) 2012, Montreal, Canada, June 2012.

J. A. Reynoso-Hernández, M. A. Pulido-Gaytan, M. C. Maya-Sánchez, J. R. Loo-Yau, “What can the ABCD Parameters Tell us About the TRL,” in Automatic Radio Frequency Technique Group (ARFTG) 2012, Montreal, Canada, June 2012.

2011

J. E. Zuñiga-Juarez, J. A. Reynoso-Hernández, M. C. Maya-Sanchez, J. R. Loo-Yau, “A Simple Procedure to Characterizing Line-Stretcher Phase Shifters,” in 77th Automatic Radio Frequency Group (ARFTG), Batimore, MD, June 2011.

2010

Susana Ortega-Cisneros, Juan J. Raygoza P., Adrian Pedroza, Miguel Carrazco, and J. R. Loo-Yau, “Design and Implementation of Self Timed and Synchronous Floating-Point Multipliers, Implemented in Reconfigurable Devices,” 1st International Congress on Instrumentation and Applied Sciences, Cancun, Mexico, October 2010.

Susana Ortega-Cisneros, Juan J. Raygoza P., Jorge Rivera D, Alí Piña R., and J. R. Loo-Yau, “Embedded System for Pollen Particle Recognition Using Microblaze Softcore,” 1st International Congress on Instrumentation and Applied Sciences, Cancun, Mexico, October 2010. 

A. García-Osorio, J. R. Loo-Yau, and J. A. Reynoso-Hernandez, “A GaN Class-F PA with 600 MHz Bandwidth and 62.5% of PAE Suitable for WiMax Frequencies,” Accepted for presentation in IEEE International Microwave Workshop Series on RF Front-ends for Software Defined and Cognitive Radio Solutions, Portugal, Aveiro, February 2010.

2009

J. A. Reynoso-Hernandez, J. R. Loo-Yau, J. E. Zuñiga-Juarez, and J. L. del Valle-Padilla, “A Straightforward Method to Determine the Parasitic Gate Resistance of GaN FET,” in International Microwave Symposium Digest, pp. 877 - 880, Boston, MA, June 2009.

J. E. Zuñiga-Juarez, J. E. Reynoso-Hernández, and J. R. Loo-Yau, “Two Tier L-L De-Embedding Method for S-Parameters Measurements of Devices Mounted in Test Fixture,” in 73th ARFTG Conference Digest, pp. 1-5, Boston, MA, June 2009.

2008

H. J. Saavedra-Gomez, J. L. del Valle, J. R. Loo-Yau, and A. García-Osorio, “A 4W UHF Si-LDMOS Class AB PA for RFID Applications,” 5th International Electrical Engineering Computing Science and Automatic Control Conference, Cd. México, pp. 252-256, November 2008.

2007

Andrés Zaráte-de Landa, J. E. Zuñiga-Juárez, J. A. Reynoso-Hernández, M. C. Maya-Sánchez, Juan Luis del Valle-Padilla, and  J. R. Loo-Yau, “An Investigation on the Modified Cold-FET Method for Determining the Gate Resistance and Inductance of the Package GaN and SiC Transistors,” 70th ARFTG Conference Digest, Tempe, Arizona, November 2007.

J. R. Loo-Yau, “High Efficiency Class E Power Ampliifer for Mobile Communications Systems,” CONCAPAN XXVII, Panamá, Panamá, Noviembre 2007.

2005

L. A. Perez-Perez, J. A. Reynoso-Hernández, and  J. R. Loo-Yau, H. Ascencio, G. Soberanes and R. Rangel-Rojo, “Detection and Mixed of Two Modulated Optical Signal Using only a Single GaAs FET (Experimental Study),” GaAs 2005, October 2005.

J. A. Reynoso-Hernández, J. R. Loo-Yau, Hugo Ascencio-Ramírez, Juan Alberto Saldivar, J. E. Zuñiga-Juárez and María del Carmen Maya-Sánchez, “Line-attenuator-line: an alternative method for in-fixture calibration,” 65th ARFTG conference digest, June 2005.

2004

J. R. Loo-Yau and J. Apolinar Reynoso, “Theoretical Study of the Effects of the Parasitic Resistance, RD and RS, on the Voltage and Current Waveform in the Transmission Line Class E PA,” 63rd ARFTG conference digest, June 2004.

2003

J.  R. Loo-Yau, J. E. Zuñiga, F. I. Hirata Flores and J. A. Reynosos Hernández, “An Improved GaAs FET Nonlinear Model Suitable for Intermodulation Analysis of Amplifiers, Switches and Resistive Mixer,”  GaAs 2003, October 2003.

2001

J. R. Loo-Yau, R. Infante Galindo  and J. A. Reynoso-Hernández, “ A New Empirical Gate Capacitance Model for PHEMT and MESFET Transistors,” 58th ARFTG conference digest, November 2001. 

Publicaciones en Congresos Nacionales

2014

Juan Antonio Reneteria Cedano, Lina María Aguilar Lobo, J. R. Loo-Yau, Susana Ortega Cisneors and Juan Jose Raygoza Pandura, “FPGA Implementation of a NARX network for modeling nonlinear systems,” in 19th Iberoamerican Congress on Pattern Recognition 2014, Puerto Vallarta, México, 2014.

2008

A. Garcia-Osorio, y J. R. Loo-Yau, “Propuesta para el Diseño de un Amplificador de Potencia Clase-F inverso de Banda Ancha Utilizando Transistores GaN”, Presentado en el Congreso Nacional de Instrumentación SOMI XXIII, Xalapa, Veracruz, Octubre 2008.

 2005

Hugo Ascencio Ramírez, J. R. Loo Yau y J. A. Reynoso-Hernández, “Diseño y Construcción de un Amplificador de Potencia Clase E de Bajo Voltaje a 1.9 GHz”, Presentado en el Congreso Nacional de Instrumentación  SOMI XX, Octubre 2005.

J. R. Loo Yau, D. A. Sanchez Herrera, J. A. Reynoso Hernández y J. E. Zuñiga Juárez, “Un Novedoso Método para Caracterizar la Distorsión en Amplitud y Fase (AM-AM y AM-PM) para Transistores Encapsulados y en Obleas”, Presentado en el Congreso de Instrumentación  SOMI XX, Octubre 2005.

2004

L. A. Pérez Pérez, J. A. Reynoso Hernández, J. R. Loo Yau y R. Rangel Rojo, “Estudio Teórico-Experimental de Mezcladores Electro-Ópticos a Base de Transistores MESFETs y PHEMTs”, Presentado en el Congreso de Instrumentación  SOMI XIX, 2004.

2000

J. R. Loo Yau, R. Infante Galindo y J. A. Reynoso Hernández, “Modelado de los Capacitares de Compuerta de Transistores PHEMTs y MESFETs por medio de un Nuevo Modelo Empírico”, Presentado en el Congreso de Instrumentación  SOMI XV, 2000.


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